1. Field of the Invention
The invention relates generally to the semiconductor power devices. More particularly, this invention relates to an improved and novel manufacturing process and device configuration for providing the split trench gates with high-density plasma (HDP) deposition oxide layer as the inter-poly oxide layer.
2. Description of the Prior Art
Conventional technologies for reducing the gate to drain capacitance Cgd in a DMOS device by employing the split trenched-gate, e.g., shielded gate trench (SGT) structure, are still confronted with technical limitations and difficulties. Specifically, trenched DMOS devices are configured with trenched gates wherein large capacitance (Cgd) between gate and drain limits the device switching speed. The capacitance is mainly generated from the electrical field coupling between the bottom of the trenched gate and the drain. In order to reduce the gate to drain capacitance, an improved split trenched-gate configuration, e.g., a Shielded Gate Trench structure (SGT), is introduced with a bottom shielding electrode at the bottom of the trenched gate to shield the trenched gates from the drain. The design concept of a SGT structure is link the bottom-shielding electrode of the trench to the source such that the trenched gates are shielded from the drain located at the bottom of the substrate as that shown in FIG. 1. A reduction of gate to drain capacitance to about half of the original Cgd value can be achieved by implementing the shielding electrode in the bottom of the trenched gates. The switching speed and switching efficiency of the DMOS devices implemented with the SGT structure are therefore greatly improved. The bottom-shielding electrode when tied to source potential provides a better shielding effect than a configuration where the bottom-shielding segment is left at a floating potential. A reduction of the gate-drain capacitance Cgd is achieved by implementing a bottom poly shielding structure. The problem of break down from trench bottom is eliminated since bottom oxide has a greater thickness than the layer gate oxide along the trench sidewalls. The net effect is an advantage that for a specific epitaxial thickness, such SGT structure can deliver much higher drain-to-source breakdown voltage (BVdss). Once the BVdss is not a limiting design consideration, the designer has the flexibilities to either increase the doping level or reduce thickness of the epitaxial layer, or to design a device that may accomplish both in order to improve the overall device performance.
However, as shown in FIG. 1, in the manufacturing process, a step of carrying out a wet etch of the first gate oxide often causes a problem of gate oxide weakness. The oxide etch often extends below the top surface of the first polysilicon that have been first deposited into the bottom part of the trench thus causing the formation of an over-etching pocket. Specifically, the sharp and thin inter-poly oxide causes early breakdown between source and gate due to the problems that 1) the dip leads to electric file concentration in the area that causes premature breakdown; and 2) the dip increases a gate-drain overlay thus the Cgd improvement is compromised. Such technical difficulties become a problem when the conventional processes are applied. When applying a conventional manufacturing process, a wet etch process is applied to remove the sidewall oxide that is damaged during first polysilicon etch-back. The isotropic wet-etch process inevitably etches off a portion of sidewall oxide slightly below the top surface of poly creating a pocket on the sidewall. A thermal oxide is grown conformal to the underlying layer forming the upper trench sidewall gate oxide and inter-poly gate oxide followed by second poly deposition. This technical problem and performance limitation often become even more severe when the cell density is increased due to the shrinking dimension of the trench openings when form the trenched power device in the semiconductor substrate.
Therefore, a need still exists in the art of power semiconductor device design and manufacture to provide new manufacturing method and device configuration in forming the power devices such that the above discussed problems and limitations can he resolved.